Recently, the requirement involving in the speed of a processor is gradually increased. For a purpose of achieving high transmission speed, the input/output (I/O) interface of a computer system needs a high bandwidth. In addition, since most electronic products are developed toward minimization, the overall volume of the chips used in the electronic products should be reduced.
Referring to FIG. 1(a), a schematic circuit block diagram of a conventional I/O interface is illustrated. The I/O interface 1 comprises an input buffer 11, an equalizer 12, a gain control circuit 13 and an output buffer 14. The input buffer 11 is employed to receive data in for example a square-wave form. Since the data are readily deteriorated during transmission, the equalizer 12 may enhance the data for various frequencies so as to improve integrity of these data. After processed by the gain control circuit 13, the data are amplified through the output buffer 14, thereby providing a large loading current to the loads such as chips.
FIG. 1(b) is a schematic circuit block diagram illustrating a conventional input buffer or output buffer, as is described in for example S. Galal, and B. Razavi, “10 Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18 μm CMOS Technology”, International Symposium on Solid-State Circuits Conference, pp. 188-189, February 2003. The input buffer 11 or the output buffer 14 shown in FIGS. 1(a) and 1(b) is a typical current mode logic (CML) buffer circuit, which includes passive inductors L1 and a normal negative active feedback circuit 110.
Please refer to FIGS. 1(c) and 1(d), which are simulation results of the buffer 11 or 14 operated in a low bandwidth (1 Gb/s) mode and a high bandwidth mode (10 Gb/s), respectively. In FIG. 1(c), the waveform of the buffer operated in the low bandwidth is substantially kept unchanged, which means a low power loss. Whereas, in the high bandwidth mode, the waveform is changed from the square wave to an approximately triangular wave, as can be seen in FIG. 1(d). The substantial distortion of data in the high bandwidth mode is undesirable. By the way, the passive inductors L1 occupy much layout area of the chip and are detrimental to minimization of the electronic product.
FIG. 1(e) is a schematic circuit block diagram illustrating a conventional equalizer, as is described for example in Yasumoto Tomita, Masaya Kibune, Junji Ogawa, and William W. Walker, “A 10 Gb/s Receiver with Equalizer and On-chip ISI Monitor in 0.11 μm CMOS”, VLSI Circuits, 2004. Digest of Technical Papers. The equalizer 12 comprises a first-stage transconductance circuit 121 and a second-stage transconductance circuit 122. The first-stage transconductance circuit 121 includes a passive capacitor Cc. The second-stage transconductance circuit 122 includes a normal negative active feedback 1221. As known, when the equalizer 12 is operated in a low bandwidth (1 Gb/s) mode, power loss of the data is still low. Whereas, in the high bandwidth mode, the waveform has substantial distortion. By the way, the passive capacitor Cc occupies much layout area of the chip and is detrimental to minimization of the electronic product.
In views of the above-described disadvantages, the applicant keeps on carving unflaggingly to develop a transmission circuit according to the present invention through wholehearted experience and research.